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Wiki source code of ACCU MB

Version 4.1 by Lars Skullerud on 2026/09/10 17:57
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1 {{wikibox title="ACCU MB" image="https://i.kym-cdn.com/photos/images/newsfeed/002/210/781/82b.jpg" caption="BOTTOM TEXT"}}
2 Voltage=24VDC
3 Fuze=Solder Bridge
4 Connector=Ampseal 23pos 17A
5 {{/wikibox}}
6
7 = Table of contents =
8
9 {{toc/}}
10
11 = Description =
12
13 The accumulator motherboard serves the purpose of connecting the IMD, BMS master, TSAL green, AIR-relays, DCDC and the car together. In addition it host AMS and IMD error signal latch, powerstages for the SDC switching of AMS and IMD signals, powerstages for AIR and precharge relays. The motherboard has a power supply for itself, the BMS, IMD and TSAL green boards and lowpass filters and voltage deviders for all the signals going to BMS and TSAL green boards.
14
15 = Design =
16
17 The motivation for using a motherboard in the accumulator is to eliminate as many wires as possible in the accumulator.
18
19 The entire form factor of the board is made to fit the IMD using nylon standoffs and bolts, the IMD is connected to the motherboard using Würth connectors and hook up wire. The TSAL green and BMS boards are connected to the motherboard using board to board connectors and the same standoffs that the IMD is connected with. This is intended to ensure the entire assembly is sufficiently stiff.
20
21 == Features ==
22
23 === Powersupply ===
24
25 {{info}}
26 This PCB uses the Align Racing default powersupply, for details see [[this>>https://www.youtube.com/watch?v=QDia3e12czc]] Wiki page.
27 {{/info}}
28
29 === Powerstages ===
30
31 All the powerstages are a high-side P-channel MOSFET switch with a N-channel MOSFET gate drive.
32
33 * N-channel: DMN65D8L-7
34 * P-channel: DMP3125L-13
35
36 There are five powerstage for
37
38 * AIR+
39 * AIR-
40 * Precharge
41 * AMS error
42 * IMD error
43
44 Powerstage layout:
45
46 [[image:powestage.png||height="273" width="240"]]
47
48 === Error latch ===
49
50 The BMS and IMD both produce a +5V digital signal to indicate "OK" state. Each signal has its own lach logic and powerstage. If the error signal is pulled to 0V the error is latched, which disables the relevant powerstage. In order to clear the error the error signal needs to go back to +5V and a error reset button has to be pressed. On startup, a RC circuit combined with a smith trigger sends a reset pulse, this is done to prevent the need for pressing the reset button each time the LV system is enabled. A demonstration of the error latch logic can be found [[here>>https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l5BOJyWoeGAmOmDsuBmSADkwDYlcQBWSGkAFgJoFMBaMMAKACVwxM-QcTqdBdOgzrUosmNS7YqBAmXAJBRBusHaA9gGsuAZyFmwZUQLkgAZgEMANsZaLIVC1cFgNZ-UYBzcEsQAmJtT0Y4OS4AY2C6FTVIsO0I9mJGaGR8YmoyCgJMKTAZGDgIGG4AJwTQ1RAENSTZMHhIN2UGlMgIkO0AemrjABdOupafTQbB4bG+JpBMYkzFzHybKXoJKGgFWsWWtZXW+C4gtgZM1UzL6-CY0zvQslur0OxWkBHqgFdXACEUQY2joAGUADR8ACKEIG0OBETAAB1jABBABCyIAjpjkQA7NqogD8xJxkBR+IpJLJ2KJVMgNPJlLc126-QsdUkvW0ZS4ACNGIxiiAOL0lgQqB1BZhZYwCDJrJgCOgOgAPUXEKjrZhsTJ4CARQTVFguEaogz4+wAB2tqOtAFPkQTjAB3ACWI1iAAt7fZ8SxHFwNQJtRtsBB1ugjSBrb9HI5fnbjHoAqjbO7HCMWNVgy9vJKosktjGAMIAESkIIFS2VSzajBkZHEebIzBE4AY6GIzBjGIAsmCBgBJfvl1HGd0BK1B2qRMR1SKidrnRchee4NQSLi2RgdlrUawtIrgPa7SCYVeHzTUQTXl6ZbdKRrNBpkbQtWajAD67vxcbGZ9niKOhnmWTIvxGX9-1+QD3BoI9PnvcChSGH8-wArhamPB5jwaZcVyCHCPxmaJtz4FoUMojYdi2Mo5D2LgwFIUJcJmE8WgkM8wGgApQmgFRtiw+VpjUK5EnwjA4DiepXzkpYTlBWB4AgNgCGyBBN0wBBVAQXoVBWLdlMqLgABNQnFY9xRQwRTJYBx4zGV0LJI+TOK4ZytAUtk1BQjpPIaYjZKgGtqFveUZHIQRlVVPNJSoKQ7wYQ1PhjPQAzYYxvT0c1jBNM1nXxAAKfKWBGbNqlRRx7C9b0WHxVFfnxOzKuMUZ7GqEYkwASh3GhljqahNwmbwz3KS9aiG4teWGxYCOkybZrUKa91OM5d3fOhFk21bktPMpYEvZyVveZs0kfDyaCWkAdrmq9hrAYaVqmGJJoGyJxK5KT-JujZTsUi7juG95qBBVaOj4UHzoQ3RH1kLYRR2eQmObG6AbR1ZfJAOyHKzNhHBYczKgYilhNeTGMc7UFvtXcmqcppcQsFXBOUwUpG0yHwQucz6PpPJc8wYPjfHyLaZBjMFy1Le09FdHMJxGewAlcIA]].
51
52 === SDC ===
53
54 There are several parts of the SDC passing through the motherboard
55
56 * DCDC 24V and ground >LVMS
57 * BSPD(HV Box)->HV Interlock
58 * HV interlock->AMS and IMD errors
59 * AMS and IMD errors->Emergency stop right
60 * TSMS->SDC end
61
62 The end of the SDC powers is the power input to the powerstages of the AIR and precharge relays. A capacitor is used to energize the coils for a short time after the SDC is broken. This is done prevent the contacts from breaking wile conducting significant current as this reduces the lifespan of the AIR relays. The capacitor charge and discharge circuit looks like this.
63
64 [[image:image.png||alt="Im sorry, but it seems Vetle has eaten the image that was supposed to go here, please bother him into making a replacement." height="257" width="352"]]
65
66 === AIR Relays ===
67
68 There are two air relays, one for the + side of the ACCU and one for the - side of the ACCU. They are energized by a powerstage activated by the BMS.
69
70 They are type: <TBA>
71
72 === Precharge Relay and logic ===
73
74 The precharge relay and logic is used to charge the car size of the hight voltage system throught a PTC resistor to 95% of the actual TS ACCU voltage before closing the second AIR relay. (Requiered by EV 5.7) This eliminates the inrush current that would otherwise occur due to charging the capacitors in the inverters.
75
76 == Pinout ==
77
78 [[image:under_construction.png||height="366" width="300"]]